Verilator open-source SystemVerilog simulator and lint system

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

SystemC Reference Implementation

RISC-V SystemC-TLM simulator

Network on Chip Simulator

This tool translates synthesizable SystemC code to synthesizable SystemVerilog.

SystemC/TLM-2.0 Co-simulation framework

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Basic RISC-V Test SoC

A modeling library with virtual components for SystemC and TLM simulators

RISC-V Virtual Prototype

QEMU libsystemctlm-soc co-simulation demos.

A SystemC productivity library: https://minres.github.io/SystemC-Components/

A Framework for Design and Verification of Image Processing Applications using UVM

Brief SystemC getting started tutorial

This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.

PCI Express controller model

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

An example of using Ramulator as memory model in a cycle-accurate SystemC Design