An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.

Unified open-source repository for OmniXtend protocol implementations in C, Verilog, and Chisel, supporting host and memory roles.

BOOM's Simulation Accelerator.

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.

An online viewer for Chipyard output files

😱 RoCC Accelerator Integration with Chipyard

End-to-end MLIR-based accelerator flow integrating Torch-MLIR, Buddy-MLIR, and Gemmini to compile and run PyTorch workloads on Gemmini accelerator implemented on an FPGA.

A high-performance, production-grade 64-bit RISC-V Multicore SoC ecosystem and industry-standard Cadence ASIC CAD flow (Genus/Innovus). Fully integrated 5-hart coherent core complex, TileLink interconnect, custom RoCC ML Systolic Array, PCIe, USB, HDMI, and silicon-proven IP blocks.

This Github repository serves as a User Guide (UG) for new Chipyard users.