Original file (957 × 430 pixels, file size: 7 KB, MIME type: image/png)

    Summary

    Description
    English: An example of how an FPGA logic cell can look like, incl a 4 inp. LUT (or two 3-LUTs), a Full Adder and a D-type Flip Flop. The 2 muxes to the right have their select signal set during the programming of the cell.
    Svenska: Exempel på hur en logisk cell i en FPGA kan vara uppbyggd, inkl. en 4-LUT (eller två 3-LUTar), en Fulladderare och en D-flip-flop. De två muxarna till höger får sina select-signaler satta vid programmeringen av cellen.
    العربية: مثال على كيفية بناء خلية منطقية في (FPGA)، تشمل (LUT) بأربع مداخل (أو اثنين من (3-LUT)، جامع كامل و (D-type Flip Flop). يتم ضبط إشارات التحديد الخاصة بالمبدّلين (muxes) الموجودين على اليمين خلال برمجة الخلية.
    Date
    Source Own work
    Author Petter.kallstrom


    This technology image could be re-created using vector graphics as a SVG file. This has several advantages; see Commons:Media for cleanup for more information. If a SVG form of this image is available, please upload it and afterwards replace this template with {{vector version available|new image name}}.
    It is recommended to name the SVG file “FPGA cell example.svg”—then the template Vector version available (or Vva) does not need the new image name parameter.

    Licensing

    Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
    In some countries this may not be legally possible; if so:
    I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

    Captions

    Add a one-line explanation of what this file represents

    Items portrayed in this file

    depicts

    creator

    some value

    Wikimedia username: Petter.kallstrom
    author name string: Petter.kallstrom
    URL: https://commons.wikimedia.org/wiki/user:Petter.kallstrom

    copyright status

    copyrighted, dedicated to the public domain by copyright holder

    copyrighted

    copyright license

    released into the public domain by the copyright holder

    inception

    2 May 2010

    source of file

    original creation by uploader

    data size

    6,699 byte

    height

    430 pixel

    width

    957 pixel

    media type

    image/png

    checksum

    b45463e743b41c83d021fac6c6eeec7aff809d46

    determination method or standard: SHA-1

    File history

    Click on a date/time to view the file as it appeared at that time.

    Date/TimeThumbnailDimensionsUserComment
    current17:20, 2 May 2010Thumbnail for version as of 17:20, 2 May 2010957 × 430 (7 KB)Petter.kallstrom{{Information |Description={{en|1=An example of how an FPGA logic cell can look like, incl a 4 inp. LUT (or two 3-LUTs), a Full Adder and a D-type Flip Flop. The 2 muxes to the right have their select signal set during the programming of the cell.}} {{sv|

    The following 2 pages use this file:

    Global file usage

    The following other wikis use this file:

    source: https://en.wikipedia.org/wiki/File:FPGA_cell_example.png